package	conv is
	subtype word8 is bit_vector(7 downto 0);
	subtype word16 is bit_vector(15 downto 0);
	subtype word32 is bit_vector(31 downto 0);
	function VECTOR_TO_INT(vec : bit_vector) return integer;
	function INT_TO_VECTOR(val : integer; size : integer := 32) return bit_vector;
	function "+" (a, b : bit_vector) return bit_vector;
end conv;

package body conv is
	function VECTOR_TO_INT(vec : bit_vector) return integer is
		variable result : integer := 0;
	begin
		for index in vec'high downto vec'low loop
			result := result * 2 + bit'pos(vec(index));
		end loop;
		return result;
	end VECTOR_TO_INT;
	
	function INT_TO_VECTOR(val : integer; size : integer := 32) return bit_vector is
		variable result : bit_vector(size-1 downto 0);
		variable value : integer := val;
		variable index : integer := 0;
	begin
		while index < size and result /= 0 loop
			result(index) := bit'val(value mod 2);
			value := value / 2;
			index := index + 1;
		end loop;
		return result;
	end INT_TO_VECTOR;
	
	function "+" (a, b : bit_vector) return bit_vector is
		variable a_size, b_size : integer;
	begin
		a_size := a'high - a'low + 1;
		b_size := b'high - b'low + 1;
		assert(a_size = b_size); 
		return INT_TO_VECTOR( VECTOR_TO_INT(a) + VECTOR_TO_INT(b), a_size );
	end "+";
end conv;

use work.conv.all;

entity test is
	port (
		sig: in bit_vector (7 downto 0);
		sigo: buffer bit_vector (7 downto 0)
	);
end test;

architecture test of test is
--signal tst : integer;
--signal bleee : bit_vector(3 downto 0);
begin
  --sigo <= INT_TO_VECTOR(tst,8);
  --tst <= VECTOR_TO_INT(sig);
  sigo <= sig + sig;
end test;